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When an external device becomes ready to be serviced by the processor the device sends a(n) _________ signal to the processor.

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Mar 1, 2020

Cards (45)

Section 1

(45 cards)

When an external device becomes ready to be serviced by the processor the device sends a(n) _________ signal to the processor.

Front

D) interrupt

Back

The concept of multiple programs taking turns in execution is known as __________.

Front

multiprogramming

Back

The two basic types of processor registers are:

Front

User-visible and Control/Status registers

Back

When a new block of data is read into the cache the __________ determines which cache location the block will occupy.

Front

mapping function

Back

One mechanism Intel uses to make its caches more effective is __________ , in which the hardware examines memory access patterns and attempts to fill the caches speculatively with data that is likely to be requested soon.

Front

prefetching

Back

The Program Status Word contains status information in the form of condition codes, which are bits typically set by the programmer as a result of program operation

Front

False

Back

A __________ organization has a number of potential advantages over a uniprocessor organization including performance, availability, incremental growth, and scaling

Front

symmetric multiprocessor

Back

The ___________ routine determines the nature of the interrupt and performs whatever actions are needed

Front

interrupt handler

Back

The _________ chooses which block to replace when a new block is to be loaded into the cache and the cache already has all slots filled with other blocks.

Front

replacement algorithm

Back

The fetched instruction is loaded into the __________

Front

Instruction Register (IR)

Back

Digital Signal Processors deal with streaming signals such as audio and video.

Front

True

Back

The four main structural elements of a computer system are:

Front

Processor, Main Memory, I/O Modules and System Bus

Back

In a uniprocessor system, multiprogramming increases processor efficiency by:

Front

Taking advantage of time wasted by long wait interrupt handling

Back

The __________ is a point-to-point link electrical interconnect specification that enables high-speed communications among connected processor chips.

Front

QPI

Back

Over the years memory access speed has consistently increased more rapidly than processor speed.

Front

False

Back

To satisfy the requirements of handheld devices, the classic microprocessor is giving way to the _________ , where not just the CPUs and caches are on the same chip, but also many of the other components of the system, such as DSPs, GPUs, I/O devices and main memory.

Front

System on a Chip (SoC

Back

Small, fast memory located between the processor and main memory is called:

Front

Cache memory

Back

A system bus transfers data between the computer and its external environment.

Front

False

Back

The fetched instruction is loaded into the Program Counter.

Front

False

Back

The interrupt can occur at any time and therefore at any point in the execution of a user program

Front

True

Back

External, nonvolatile memory is also referred to as __________ or auxiliary memory

Front

secondary memory

Back

The __________ holds the address of the next instruction to be fetched

Front

Program Counter (PC)

Back

Instruction processing consists of two steps:

Front

fetch and execute

Back

A special type of address register required by a system that implements user visible stack addressing is called a __________ .

Front

stack pointer

Back

Interrupts are provided primarily as a way to improve processor utilization.

Front

True

Back

The __________ contains the data to be written into memory and receives the data read from memory.

Front

memory buffer register

Back

An example of a multicore system is the Intel Core i7.

Front

True

Back

In a two-level memory hierarchy the Hit Ratio is defined as the fraction of all memory accesses found in the slower memory.

Front

False

Back

The invention of the _________ was the hardware revolution that brought about desktop and handheld computing

Front

m icroprocessor

Back

A Control/Status register that contains the address of the next instruction to be fetched is called the ______

Front

program Counter (PC)

Back

The unit of data exchanged between cache and main memory is __________

Front

block size

Back

The __________ is a device for staging the movement of data between main memory and processor registers to improve performance and is not usually visible to the programmer or processor.

Front

cache

Back

With interrupts, the processor can not be engaged in executing other instructions while an I/O operation is in progress.

Front

False

Back

In a _________ multiprocessor all processors can perform the same functions so the failure of a single processor does not halt the machine.

Front

symmetric

Back

Cache memory is invisible to the OS.

Front

True

Back

__________ is more efficient than interrupt-driven or programmed I/O for a multiple-word I/O transfer.

Front

Direct memory access

Back

A __________ computer combines two or more processors on a single piece of silicon.

Front

multicore

Back

When an external device is ready to accept more data from the processor, the I/O module for that external device sends an __________ signal to the processor.

Front

interrupt request

Back

The processing required for a single instruction is called a(n) __________ cycle.

Front

instruction

Back

Registers that are used by system programs to minimize main memory references by optimizing register use are called __________ .

Front

user-visible registers

Back

The processor controls the operation of the computer and performs its data processing functions.

Front

True

Back

The operating system acts as an interface between the computer hardware and the human user.

Front

True

Back

It is not possible for a communications interrupt to occur while a printer interrupt is being processed

Front

False

Back

An SMP can be defined as a stand-alone computer system with two or more similar processors of comparable capability.

Front

True

Back

Each location in Main Memory contains a _________ value that can be interpreted as either an instruction or data

Front

binary number

Back